RE: 4-bit MISC CPU ISA 04-15-2018, 06:29 AM
#5
(04-15-2018, 06:22 AM)Ender Wrote:(04-15-2018, 06:17 AM)phyrrus9 Wrote:(04-15-2018, 06:12 AM)Ender Wrote: I'm interested, seems neat, I want one, and I'll probably help.
Note: This idea came from the One Page Computing Challenge that I found on Hackaday: https://hackaday.io/project/25091-one-pa...-challenge
I'll probably also make my own separate small design that'll never be hardware, but eh
lol.....this whole time I thought they meant that the schematic had to fit on one piece of paper.....looks like they aren't talking about schematics though, since this is for an FPGA they're either talking Verilog HDL or LUT in-mem
"To keep it fun, make up your own idea of what that means - one page of spec, or one page of schematic, or one page of HDL, or a one-page emulator in the language of your choice."
"And if you want to define one page as a huge page with tiny font, go ahead! Personally I'm more interested in the 66-line fanfold paper, which is I think 132 characters across. I hope not to code-golf, so the code is remains readable and self-explanatory. I just might allow myself to print at 8 lines per inch, and get 88 lines to the page."
Example: https://github.com/revaldinho/opc/tree/master <-- a thing from a guy
Well....technically that is easy. Here's the MISC CPU that evolved into the one this thread is about:

























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