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4-bit MISC CPU ISA - Printable Version

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4-bit MISC CPU ISA - phyrrus9 - 04-15-2018

So, if you havent read Introduction to CPU Design, you should read it, or else you won't understand this at all.

So, short story, while working on CPU-RISC a little I decided I wanted something that's in a smaller package and runs at a higher frequency. To get that, I simply cut the bus width to 4 bits and moved to an ISA that was small enough to use without a pipeline. Here it is:
[Image: HehjUlh.png]

The cache is 128-bit, meaning it holds 16 instructions, each memory segment is a 16-bit address, and each segment contains 16 instructions. This makes a total of 4,096 instructions that can be held in RAM at any time.

Coprocessor support is enabled with the use of a coprocessor enable flag that is exposed to the silicon, and up to 15 coprocessors per CPU. Two registers exist on each coprocessor (or between different CPUs) to store and retrieve data from them, and these registers can be accessed with special instructions. After loading the required data to a coprocessor register, the pipeline enable pin is driven low, the coprocessor enable pin is driven high and the coprocessor address is placed on the bus. When the coprocessor completes its operation, it reverses the former and the CPU begins executing instructions again.

Target package size: DIP-24
[Image: GYuNXbg.png]

Let me know what you think, if you want one when it's finished, and if you want to contribute.

@"Ender" you should work on this....

RE: 4-bit MISC CPU ISA - Blink - 04-15-2018

I'm interested, seems neat, I want one, and I'll probably help.

Note: This idea came from the One Page Computing Challenge that I found on Hackaday: https://hackaday.io/project/25091-one-page-computing-challenge
I'll probably also make my own separate small design that'll never be hardware, but eh

RE: 4-bit MISC CPU ISA - phyrrus9 - 04-15-2018

(04-15-2018, 06:12 AM)Ender Wrote: I'm interested, seems neat, I want one, and I'll probably help.

Note: This idea came from the One Page Computing Challenge that I found on Hackaday: https://hackaday.io/project/25091-one-page-computing-challenge
I'll probably also make my own separate small design that'll never be hardware, but eh

lol.....this whole time I thought they meant that the schematic had to fit on one piece of paper.....looks like they aren't talking about schematics though, since this is for an FPGA they're either talking Verilog HDL or LUT in-mem

RE: 4-bit MISC CPU ISA - Blink - 04-15-2018

(04-15-2018, 06:17 AM)phyrrus9 Wrote:
(04-15-2018, 06:12 AM)Ender Wrote: I'm interested, seems neat, I want one, and I'll probably help.

Note: This idea came from the One Page Computing Challenge that I found on Hackaday: https://hackaday.io/project/25091-one-page-computing-challenge
I'll probably also make my own separate small design that'll never be hardware, but eh

lol.....this whole time I thought they meant that the schematic had to fit on one piece of paper.....looks like they aren't talking about schematics though, since this is for an FPGA they're either talking Verilog HDL or LUT in-mem

"To keep it fun, make up your own idea of what that means - one page of spec, or one page of schematic, or one page of HDL, or a one-page emulator in the language of your choice."
"And if you want to define one page as a huge page with tiny font, go ahead! Personally I'm more interested in the 66-line fanfold paper, which is I think 132 characters across. I hope not to code-golf, so the code is remains readable and self-explanatory. I just might allow myself to print at 8 lines per inch, and get 88 lines to the page."

Example: https://github.com/revaldinho/opc/tree/master <-- a thing from a guy

RE: 4-bit MISC CPU ISA - phyrrus9 - 04-15-2018

(04-15-2018, 06:22 AM)Ender Wrote:
(04-15-2018, 06:17 AM)phyrrus9 Wrote:
(04-15-2018, 06:12 AM)Ender Wrote: I'm interested, seems neat, I want one, and I'll probably help.

Note: This idea came from the One Page Computing Challenge that I found on Hackaday: https://hackaday.io/project/25091-one-page-computing-challenge
I'll probably also make my own separate small design that'll never be hardware, but eh

lol.....this whole time I thought they meant that the schematic had to fit on one piece of paper.....looks like they aren't talking about schematics though, since this is for an FPGA they're either talking Verilog HDL or LUT in-mem

"To keep it fun, make up your own idea of what that means - one page of spec, or one page of schematic, or one page of HDL, or a one-page emulator in the language of your choice."
"And if you want to define one page as a huge page with tiny font, go ahead! Personally I'm more interested in the 66-line fanfold paper, which is I think 132 characters across. I hope not to code-golf, so the code is remains readable and self-explanatory. I just might allow myself to print at 8 lines per inch, and get 88 lines to the page."

Example: https://github.com/revaldinho/opc/tree/master <-- a thing from a guy

Well....technically that is easy. Here's the MISC CPU that evolved into the one this thread is about:
[Image: uCRYtrV.png]

RE: 4-bit MISC CPU ISA - Blink - 04-15-2018

(04-15-2018, 06:29 AM)phyrrus9 Wrote:
(04-15-2018, 06:22 AM)Ender Wrote:
(04-15-2018, 06:17 AM)phyrrus9 Wrote: lol.....this whole time I thought they meant that the schematic had to fit on one piece of paper.....looks like they aren't talking about schematics though, since this is for an FPGA they're either talking Verilog HDL or LUT in-mem

"To keep it fun, make up your own idea of what that means - one page of spec, or one page of schematic, or one page of HDL, or a one-page emulator in the language of your choice."
"And if you want to define one page as a huge page with tiny font, go ahead! Personally I'm more interested in the 66-line fanfold paper, which is I think 132 characters across. I hope not to code-golf, so the code is remains readable and self-explanatory. I just might allow myself to print at 8 lines per inch, and get 88 lines to the page."

Example: https://github.com/revaldinho/opc/tree/master <-- a thing from a guy

Well....technically that is easy. Here's the MISC CPU that evolved into the one this thread is about:
[Image: uCRYtrV.png]

Why not Quartus instead of Logisim?
Also some other guy in the comments also gave a diagram...
Spoiler:
[Image: 16130_CPU.JPG]


And hardware:
[Image: 2663081469667843366.JPG]

RE: 4-bit MISC CPU ISA - phyrrus9 - 04-15-2018

(04-15-2018, 06:36 AM)Ender Wrote: Why not Quartus instead of Logisim?

Didn't have a license at the time....that's a VERY old drawing