[phyrrus9]

So, if you havent read Introduction to CPU Design, you should read it, or else you won't understand this at all.

So, short story, while working on CPU-RISC a little I decided I wanted something that's in a smaller package and runs at a higher frequency. To get that, I simply cut the bus width to 4 bits and moved to an ISA that was small enough to use without a pipeline. Here it is:


The cache is 128-bit, meaning it holds 16 instructions, each memory segment is a 16-bit address, and each segment contains 16 instructions. This makes a total of 4,096 instructions that can be held in RAM at any time.

Coprocessor support is enabled with the use of a coprocessor enable flag that is exposed to the silicon, and up to 15 coprocessors per CPU. Two registers exist on each coprocessor (or between different CPUs) to store and retrieve data from them, and these registers can be accessed with special instructions. After loading the required data to a coprocessor register, the pipeline enable pin is driven low, the coprocessor enable pin is driven high and the coprocessor address is placed on the bus. When the coprocessor completes its operation, it reverses the former and the CPU begins executing instructions again.

Target package size: DIP-24


Let me know what you think, if you want one when it's finished, and if you want to contribute.

@"Ender" you should work on this....