[phyrrus9]

That was nice. You should've explained what LDR and STR do so us Intel-users can understand what's happening.

To Intel People:
As stated earlier, they change based on the flags set and stuff, but in this case, LDR loads a register (specified by Rd) with a value from a memory address relative to a register, and STR loads memory relative to a register with the contents of the register specified by Rd.
(Rd changes places from right to left in the assembly code, so it'll make more sense for the programmer)

LDR = LoaD Register
STR = STore Register

Probably should have mentioned that RISC is load-store arch. Intel let's you do this with MOV instructions, which isn't a possibility with these setups. There are only a few instructions that can access memory. LDR and STR are the most important two.

For those who want a little more reading on the subject, here is the ARM infodoc on these instructions. The link is for the M3, but it's the same instruction. We'll be working with the first format:

Code:

op{type}{cond} Rt, [Rn {, #offset}]        ; immediate offset

For our example, the type is always WORD, so we don't fill that field in.