Full Version: IGFET and CMOS
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This isn't going to be a real tutorial series, it has no clear objective, and I'll just be releasing these as supplemental information for anyone interested in computer engineering. So, let's start off with the terms. We're going to talk about IGFET and CMOS in this thread. So, what do they stand for?

IGFET: Insulated Gate Field Effect Transistor, commonly referred to as a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). These are usually 4 pin transistors, with pins for Source, Gate, Drain, and Substrate (which is usually connected internally to the Source). They're voltage triggered transistors (comparative to the Bipolar Junction Transistor, which is current driven), and so they are very power effective (using next to no power) and efficient in terms of speed.

CMOS: Complementary Metal-Oxide Semiconductor, meaning basically that you use inverted logic beside regular logic to create your device.

Let's take a look at a CMOS NOT gate made with MOSFETs:
[Image: 1VsOHik.png]
Here you can see that both n-MOSFET and p-MOSFET are used here. If we flip the input, it all makes sense
[Image: CLbH9Hs.png]

Now, I want to keep these brief, so I won't actually be explaining most of what these all do, its up to you to research that stuff on your own time. Here's the 3 basic gates: AND, NOT, and OR:
[Image: cMkxJfc.png]

So, these gates should all be familiar to you from Intro to CPU Design. The purpose of showing you how they are made is so that you will be able to optimize your schematics after you have tested them, so that you can lower your transistor count and increase your clock rates. Now, with these 3 logic gates we can build any other logic gate, without having to do optimization (these are simplest form).

The next 2 we need are NAND and NOR. These are pretty simple, just invert the output of the gate, so we take our AND and OR gates and wire Q to A in a NOT gate, then clean it up. The finished results look something like this:
[Image: fd7lslg.png]
Take note that these are both 4-transistor gates. This knowledge will come in handy when you build your circuits later in your development process.

Now, let's explore the possibility of creating some more advanced gates. XOR and XNOR. I played around with them for a few hours and kept coming up with a gate that was too complex, but eventually made these:
[Image: mwLFbYQ.png]
You'll see that they do indeed function, but they are 8 and 10 transistors respectively. Now, that's a massive increase from our 4-transistor gates, please keep that in mind.

So, how does this all relate to CMOS?
Well, knowing how many transistors you need for each logic operation is key in how you make your board. Ideally you want to surface mount blocks of transistors so that you can just wire them with traces in different board levels. Understanding the limitations of each gate will help you with that, and using CMOS technology you can reduce it further. If you have a positive and an inverted signal for every input to a 4+ transistor gate, then you can optimize them down. Secondly, adding more inputs to these gates is simpler and you save transistors by doing it at this level.

This is where I'm going to leave off for today, let me know if you have questions.