Why CMOS is a PITA 04-18-2018, 02:39 PM
#1
So, I started talking about IGFETs and CMOS the other day, and just went back to play a little more. Basically there are 4 rules to making a CMOS circuit:
So, sounds simple enough, right? Yeah, until you try to implement a basic AND gate and realize its not possible. I want you to take a look at this AND2 gate and tell me if it looks familiar to you:
![[Image: P7r8feR.png]](https://i.imgur.com/P7r8feR.png)
Well it should, because that's not actually an AND gate, it's a NOT NOT AND gate...... For some comparison, here's a NAND (NOT AND) gate:
![[Image: xR9nzwD.png]](https://i.imgur.com/xR9nzwD.png)
Still not getting it? I'll put them side by side for you....
![[Image: evVFfYS.png]](https://i.imgur.com/evVFfYS.png)
And that's why its a fucking pain in the ass.....
- Only pull down with n-channel FETs
- Only pull up with p-channel FETs
- Never pull up and down simultaneously
- Always pull the output
So, sounds simple enough, right? Yeah, until you try to implement a basic AND gate and realize its not possible. I want you to take a look at this AND2 gate and tell me if it looks familiar to you:
![[Image: P7r8feR.png]](https://i.imgur.com/P7r8feR.png)
Well it should, because that's not actually an AND gate, it's a NOT NOT AND gate...... For some comparison, here's a NAND (NOT AND) gate:
![[Image: xR9nzwD.png]](https://i.imgur.com/xR9nzwD.png)
Still not getting it? I'll put them side by side for you....
![[Image: evVFfYS.png]](https://i.imgur.com/evVFfYS.png)
And that's why its a fucking pain in the ass.....

























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