Tutorial Intro to CPU design [Part 4: the setup] filter_list Author Message
Intro to CPU design [Part 4: the setup] #1
Like before... part 3 is here

Okay, so I still don't really want to do a crapload of math and hope you catch on, so we will spend this tutorial designing and learning the parts for our CPU.

Here is what we will need (this will be explained)
• Memory block
• CPU Registers
• Instruction block
• ALU
• MMU
• Instruction fetcher
• Instruction decoder
• Clock generator

Okay, so let's describe what all of those do and why we need them:

Memory block:
On a basic CPU, this isn't needed, but for the sake of learning something new and passing it on, I will include the ability to read and write from memory. Consider this RAM.

CPU registers:
These are the A, B, X, and IP storage units. They are variables (if you know programming or basic algebra). Since everything we do here will be using wires and some transistor gates, we will need to implement a way to store data. We will use a D latch in blocks. My drawings have all of these schematics already drawn out. They will be explained when they are brought up.

Instruction block:
This is known as a L1 cache on modern CPUs, normally the instructions are read from RAM into the cache and executed from there. Since we are limited by space and I wanted to maximize how much memory we can use, we will have 8 bytes of memory, AND 8 bytes of instruction storage. This totals 16 bytes of "memory", plus the four nibble-wide registers, meaning there is 18 bytes of storage on our CPU total.

ALU:
The ALU (Arithmatic and Logic unit) is a sub-cpu that will handle all of our mathematical operations. We will also have a separate MMU that will handle all of our memory accesses.

MMU:
The MMU (Memory Management Unit) will be the unit that handles our memory access. It will be separate from the ALU but it will work in tandem. This idea may be scrapped later if it becomes too complicated for this tutorial. Most CPUs have many of these, and it contributes to the modular design of the CPU.

Instruction fetcher:
The instruction fetcher will read from the instruction block and decide which byte to pull and send to the instruction decoder. This will also be responsible for updating the IP.

Instruction decoder:
The decoder will decipher the CPU level instruction and determine if an ALU operation, a MMU operation, or a register operation needs to be done, and convert the instruction into the instruction set of either the ALU or MMU.

Clock generator:
Okay, this is where it will get tricky, we will be using a human-input clock. This means we will wire up a button, each downpress will perform the following pipe stages:
Fetch
Decode
and each release will perform:
Execute
Write-back

Note, the pipe design may change as we continue this project. It might be required that the pipe look more like this:
Write-back
Fetch
and
Decode
Execute

This way, you will be able to watch the states of the CPU as they are executed stage by stage.

We will also be wiring up 144 LED's so that you can see the memory block, instruction block, A, B, X, and IP
This part is optional, but it is nice to see what is going on.

If you get really good at multiplexers, you can get away with using 7 switches, and 4 LEDs.
While we are at it, what is a multiplexer?

A multiplexer is a function that takes a number of inputs and returns one output.

f(a, b, c, d, s, t) -> q

follows the table below:
Code:
```s|t|q 0|0|a 0|1|b 1|0|c 1|1|d```

There will be a curcuit drawing when we get more into them.

Stay tuned for part 5!

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